The invention relates generally to integrated circuit fabrication and, in particular, to chips with pads and methods for processing the pads of chips.
A chip or die includes integrated circuits formed by front-end-of-line processing of a wafer, a local interconnect layer formed by middle-end-of-line processing, and an interconnect structure comprising a stack of metallization levels formed by back-end-of line processing. Multiple chips can be fabricated on the same wafer. A topmost metallization level includes bond pads that provide electrical access points to the integrated circuits of the chip. During chip packaging, the bond pads on the chip are physically and electrically connected by solder bumps or wire bonds with matching pads on a substrate, such as a printed circuit board. These connections supply electrical pathways for transferring data signals to and from the integrated circuits to an external device, such as a computing system, and electrical pathways for powering the integrated circuits.
The individual integrated circuits of each semiconductor chip on a wafer may be tested to detect functional defects before die preparation and packaging. The bond pads may be used electrical access locations to the integrated circuits of the chip during testing. To avoid damaging the bond pads, the topmost metallization level may include probe pads that also provide electrical access locations to the integrated circuits, but that are not used during bonding.
The testing may be performed by automated test equipment, known as a wafer prober, and involved contact with some form of mechanical probe. Typically, mechanical probes are arranged on a probe card, which is attached to the wafer prober. The wafer may be lifted by the wafer prober until the bond pads or probe pads connected with one or more integrated circuits of a chip on the wafer make physical contact with the mechanical probes.
Improved chips with pads and methods for processing the pads of chips are needed.